Very Large Scale integration (VLSI) Design

UCERD Rawalpindi
UCERD Islamabad
UCERD Murree
Past Present and Future of Integrated Circuits

Introduction to VLSI
Classification of ICs
Design Flow (Y-Map)
Fabrication Process
  VLSI Components and Architectures

Bipolar Technologies
  MOS Transistor Theory


Power (static , dynamic power)

Types of Integrated Circuits
Switch/Transistor Level Circuit Design
Gate Level Design
   Combinational Logic Circuits
RTL (Register Transfer Level Design)
   Multiplexer, Encoder, Decoder,  State Machine, Orbiter and Scheduler
Abstract Level Design
Tools:  ROCCC, C2HDL LEGUP, Vivado, Quartus, Modelsim

Processor and Memory
Components: ALU, Buses, Registers etc.

System on Chip Design I
Using processors, caches, buses etc.

System on Chip Design II
Multi Processor System Design

Basic Circuits Design Concept

Ultra-Fast VLSI Circuits and System and their Design
Gallium arsenide, Graphene etc.
Ultra-Fast VLSI Circuits and System and their Design
3D Fabrication
Ultra-Fast VLSI Circuits and System and their Design
3D FPGA i.e Tabaula etc
Analog Circuit Design (Field Programmable Analog Arrays) FPAA
VLSI Design course emphasizes on imparting overall exposure to the concept and design methodologies of all significant aspects of VLSI engineering relevant to the industry needs. The program offers in-depth, hands-on training on various design methods such as gate level, register transfer level, abstract level designs, etc. At the end of the course, the student can understand the VLSI manufacturing processor, solve a real-world problems and map and port these issues in an integrated circuit.
At the end of my course, students should learn:
To identify the Physical Layout and Gate Level System Design using 65 nm ASIC technology.
To discuss a scalar RISC core and Application-Specific Hardware Accelerators.
To design and program Uni-core System on Chip (SoC) and Multi-core (SoC) architectures. Bus System Performance (data rate), Processor Performance (FLOPS), Memory Read Write Time.
To use an FPGA logic block for gate and switch level systems.
To develop a layout of semi custom ASIC logic cell of three input lookup table (LUT), an FPGA Configurable Logic Block (CLB by using VLSI Digital Schematic Editor & Simulator.
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Lectures and Material