UCERD Gathering Intellectuals Fostering Innovations
Unal Center of Educaiton Research & Development
Unal Center of Educaiton Research & Development
UCERD Rawalpindi
Supercomputing Center
UCERD Murree
Over the past few years, the dominion of digital systems has expanded to a wide variety of products, including digital cameras, sensor networks, medical imaging systems, automotive, robotics and communication systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Increasing system complexity has created a pressing need for better design tools and associated methodologies and languages for meeting the stringent time to market and cost constraints. Platform-centric and platform based system-on-chip (SoC) design methodologies, based on reuse of software and hardware functionality, has also gained increasing exposure and usage within the Electronic System-Level (ESL) design communities. FPGAs are compelling platforms for hardware acceleration of embedded systems. These devices, by virtue of their massively parallel structures, provide embedded systems designers with new alternatives for creating high performance applications. However, there are confronts to using FPGAs as software platforms. Historically, low-level hardware descriptions (fixed architecture) must be written in VHDL or Verilog, languages that are not generally part of a software programmer's expertise.
Mega-gate FPGAs now allow complete digital systems to be implemented on a single reconfigurable logic chip, including soft-core or hardcore processors – so-called reconfigurable system-on-chip (rSoC). Because soft-core processors are implemented on a configurable logic fabric, they are not as area and power efficient as fixed microprocessors implemented directly on custom integrated circuits. The advantage of soft-core processors is that they can be modified, on an application by application basis, to better fit the requirements of that particular application.
C-to-hardware tool can abstract away many of the details of hardware-to-software communication, allowing us to focus on application partitioning without having to worry about the low-level details of the hardware.
Although such tools can dramatically improve your ability to create FPGA-based applications, but for the highest performance you still need to understand certain aspects of the underlying hardware. Challenges in the development of these tools are to decide how and when to partition complex applications between hardware and software and how to structure an application to take full benefits of FPGA. In order to meet these challenges, careful consideration of following partitioning decisions and C coding styles are the key players to take maximum advantage of hardware parallelism.
As capability of modern SRAM-based FPGAs, IP Reusability, Soft Core peripherals and gate counts increase with each new generation of FPGAs, it becomes necessary to implement a tool “C to FPGA” for Digital Systems.
The key research questions to be investigated in this research are:
Allocation: Determine the number of resources that have been allocated or allotted to synthesize the hardware circuit.
Scheduling: Settle on the time step or clock cycle in which each operation in the design executes.
Module Selection: Decide resource type from the resource library that a process carries out.
Binding: Find out best solution for mapping between the operations, variables and data transfers in the design and the specific resources in the resource allocation.
Control Generation and Optimization: Try to minimize the size of control unit and hence improve metrics such as area and power.
Mega-gate FPGAs now allow complete digital systems to be implemented on a single reconfigurable logic chip, including soft-core or hardcore processors – so-called reconfigurable system-on-chip (rSoC). Because soft-core processors are implemented on a configurable logic fabric, they are not as area and power efficient as fixed microprocessors implemented directly on custom integrated circuits. The advantage of soft-core processors is that they can be modified, on an application by application basis, to better fit the requirements of that particular application.
C-to-hardware tool can abstract away many of the details of hardware-to-software communication, allowing us to focus on application partitioning without having to worry about the low-level details of the hardware.
Although such tools can dramatically improve your ability to create FPGA-based applications, but for the highest performance you still need to understand certain aspects of the underlying hardware. Challenges in the development of these tools are to decide how and when to partition complex applications between hardware and software and how to structure an application to take full benefits of FPGA. In order to meet these challenges, careful consideration of following partitioning decisions and C coding styles are the key players to take maximum advantage of hardware parallelism.
As capability of modern SRAM-based FPGAs, IP Reusability, Soft Core peripherals and gate counts increase with each new generation of FPGAs, it becomes necessary to implement a tool “C to FPGA” for Digital Systems.
The key research questions to be investigated in this research are:
Allocation: Determine the number of resources that have been allocated or allotted to synthesize the hardware circuit.
Scheduling: Settle on the time step or clock cycle in which each operation in the design executes.
Module Selection: Decide resource type from the resource library that a process carries out.
Binding: Find out best solution for mapping between the operations, variables and data transfers in the design and the specific resources in the resource allocation.
Control Generation and Optimization: Try to minimize the size of control unit and hence improve metrics such as area and power.
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Dr. Tassadaq Hussain.
He is a permanent faculty member at, Riphah International University.
He did his Ph.D. from Barcelona-tech Spain, in collaboration with Barcelona Supercomputing Center and Microsoft Research Center.
He is a member of HiPEAC: European Network on High Performance and Embedded Architecture and Compilation, Barcelona Supercomputing Center and Microsoft ResearchCentre Spain.
Until January 2018, he had more than 14 years of industrial experience including, Barcelona Supercomputing Centre Spain, Infineon technology France, Microsoft Research Cambridge, PLDA Italia, IBM Zurich Switzerland, and REPSOL Spain. He has published more than 50 international publications and filed 5 patents.
Tassadaq's main research lines are Machine Learning, Parallel Programming, Heterogeneous Multi-core Architectures, Single board Computers, Embedded Computer Vision, Runtime Resource Aware Architectures, Software Defined Radio and Supercomputing for Artificial Intelligence and Scientific Computing.
www.tassadaq.ucerd.com
He is a permanent faculty member at, Riphah International University.
He did his Ph.D. from Barcelona-tech Spain, in collaboration with Barcelona Supercomputing Center and Microsoft Research Center.
He is a member of HiPEAC: European Network on High Performance and Embedded Architecture and Compilation, Barcelona Supercomputing Center and Microsoft ResearchCentre Spain.
Until January 2018, he had more than 14 years of industrial experience including, Barcelona Supercomputing Centre Spain, Infineon technology France, Microsoft Research Cambridge, PLDA Italia, IBM Zurich Switzerland, and REPSOL Spain. He has published more than 50 international publications and filed 5 patents.
Tassadaq's main research lines are Machine Learning, Parallel Programming, Heterogeneous Multi-core Architectures, Single board Computers, Embedded Computer Vision, Runtime Resource Aware Architectures, Software Defined Radio and Supercomputing for Artificial Intelligence and Scientific Computing.
www.tassadaq.ucerd.com