VLSI System Design Using High Level Synthesis Tools

The electronic forum deals with the topics related to analog and digital circuits and systems (i.e. ASIC, FPGA, DSPs, Microcontroller, Single/Multi Processors etc) and their programming such as HDL, C/C++, etc.
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The electronic forum deals with the topics related to analog and digital circuits and systems (i.e. ASIC, FPGA, DSPs, Microcontroller, Single/Multi Processors, PCBs etc) and their programming such as HDL, C/C++, etc.

VLSI System Design Using High Level Synthesis Tools

Unread postby UCERD.COM » Thu Mar 26, 2015 6:19 am

Modern digital electronics courses usually include hardware description languages as a useful tool to implement relatively complex digital designs using programmable logic devices. These languages are close to the final hardware architecture, but usually lead to long and complex design procedures. To overcome this limitation, high level synthesis tools provide an intuitive and straight-forward design flow using well-known programming languages such as C. This work deals with the inclusion in a digital electronics course high-level synthesis tools to provide the student with a wider vision and additional design tools.


Select an application HLS and hand written (VHDL, Verilog) and compare results (mentioned below) of both designs.

Number of Lines of Code:
Resource allocation (LUTs, Regs):
Maximum Operating Frequency:
Power Consumptions using (Static Power):
If you want you can add some more comparisons here:


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